A double data rate (DDR) memory controller can be implemented in a field programmable gate array (FPGA) device. As the DDR memory is advanced to provide higher data throughput, e.g., up to 1 Gbs, a timing budget left for the FPGA is substantially reduced. The DDR memory interface is defined to transmit a data strobe signal in conjunction with a group of data signals for data capture in the receiver side, i.e., at the memory controller of the FPGA. All skew and jitter among the various data signals and the data strobe signal is treated as uncertainty and is subtracted from the valid data sampling window. Thus, uncertainty associated with signal skew limits the rate at which the memory controller can process incoming and outgoing data transmissions. Therefore, it is desirable to reduce skew among the data signals and data strobe signal. In view of the foregoing, a solution is needed to accurately quantify skew between signals and accurately compensate for the quantified skew to enhance device performance.